Computer systems such as servers typically employ many dynamic random access memory (DRAM) chips in order to have adequate memory capacity. Each of these DRAM chips has a delay-locked loop (DLL) that synchronizes the data output of the DRAM with an external clock at a clock input of the DRAM chip. Because only a few DRAM chips are accessed at any given time, a large number of DRAM chips are in idle mode. While unused DRAM chips can potentially turn off their DLLs to save power, their turn-on time would be significantly high due to the need for re-locking their DLLs. To avoid such latency, idling DRAMs usually keep their DLLs on.